The present invention relates generally to integrated circuit designs and more particularly to write circuit design for improving write margins in static random access memory (SRAM).
SRAM is typically used for storing data needed to be speed accessed by processing units. A conventional 6-T SRAM cell comprises two cross-coupled inverters forming a data latch and two pass-gate NMOS transistors for controlling accesses to the data latch by a bit-line-true (BLT) and a bit-line-complementary (BLC). During a read operation, the data latch drives the BLT or BLC to develop a differential voltage between the BLT and BLC, therefore a higher supply voltage provides a greater read margin. During a write operation, it is the BLT or BLC that forces the data latch to flip, therefore, given a fixed BLT and BLC voltage level, a lower supply voltage provides a greater write margin.
There have been many attempts to increase write margins in the SRAM, such as floating a column of SRAM cells that is being written. However, power supply lines of the SRAM may have large capacitances, even though the outside power supply is switched off, the large capacitances may store charges that prevent the power supply line voltage from dropping any significant amount during the write cycle. Especially when the SRAM speed becomes very fast with a very short write cycle, the floating power supply method may not be very effective in improving a write margin of the SRAM.
As such, what is desired is a SRAM cell power supply system that discharges the power supply lines during a write operation.